期末上機考

12/2 and/or/not閘與and/or/not閘轉nand/nor閘

and/or/not閘↑
module top;

wire A, B, C, D, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

and a1(a5, A, a3, a4);
not n1(a1, A)

and a2(a6, a1, a2, D);
not n2(a2, B);

and a3(a7, B, a3, a4);
not n3(a3, C);

and a4(a8, C, D);
not n4(a4, D);

or o1(F, a5, a6, a7, a8);

endmodule

module system_clock(clk)
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk;
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

nand閘↑

module top; 

wire A, B, C, D, F;

system_clock #800 clock1(A); 

system_clock #400 clock2(B);

system_clock #200 clock3(C);

system_clock #100 clock4(D);

nand(a1, A, A);

nand(a2, B, B);

nand(a3, C, C);

nand(a4, D, D);

nand(b1, A, a3, a4);

nand(c1, b1, b1);

nand(b2, a1, a2, D);

nand(c2, b2, b2)

nand(b3, B, a3, a4);

nand(c3, b3, b3);

nand(b4, C, D);

nand(c4, b4, b4);

nand(d1, c1, c1);

nand(d2, c2, c2);

nand(d3, c3, c3);

nand(d4, c4, c4);

nand(F, d1, d2, d3, d4);

endmodule 

module system_clock(clk); 

parameter PERIOD=100; 

output clk; 

reg clk; 

initial clk=0; 

always 

 begin 

#(PERIOD/2) clk=~clk

 end 

always@(posedge clk)

 if($time>1000)$stop; 

endmodule 

 nor閘↑
module top;

wire A, B, C, D, F;
system_clock #800 clock1(A);
system_clock #400 clock2(B);
system_clock #200 clock3(C);
system_clock #100 clock4(D);

nor(a1, A, A);
nor(a2, B, B);
nor(a3, C, C)
nor(a4, D, D);
nor(b1, A, A);
nor(b2, a3, a3);
nor(b3, a4, a4);
nor(g1, b1, b2, b3);
nor(c1, a1, a1);
nor(c2, a2, a2);
nor(c3, D, D);
nor(g2, c1, c2, c3);
nor(d1, B, B);
nor(d2, a3, a3);
nor(d3, a4, a4);
nor(g3, d1, d2, d3);
nor(e1, C, C);
nor(e2, D, D);
nor(g4, e1, e2);
nor(h1, g1, g2, g3, g4);
nor(F, h1, h1);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;

initial clk=0;

always
 begin
#(PERIOD/2) clk=~clk
 end

always@(posedge clk)
 if($time>1000)$stop;

endmodule

11/25三位元全加法器-行為

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;

assign{c_out,sum}=a+b+c_in;
endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

11/25三位元全加法器-結構

module fulladder (sum, c_out, a, b, c_in);
wire s1, c1, c2;
output sum;
output c_out;
input a, b, c_in;
xor g1(s1, a, b);
xor g2(sum, s1, c_in);
and g3(c1, a,b);
and g4(c2, s1, c_in) ;
xor g5(c_out, c2, c1) ;

endmodule

module adder3(sum, c_out, a, b, c_in);
wire [2:0] c;
output [2:0] sum;
output c_out;
input [2:0] a;
input [2:0] b;
input c_in;
fulladder fa1(sum[0], c[1], a[0], b[0], c_in) ;
fulladder fa2(sum[1], c[2], a[1], b[1], c[1]) ;
fulladder fa3(sum[2], c_out, a[2], b[2], c[2]) ;


endmodule

module main;
reg [2:0] a;
reg [2:0] b;
wire [2:0] sum;
wire c_out;

adder3 DUT (sum, c_out, a, b, 1'b0);

initial
begin
  a = 4'b0101;
  b = 4'b0000;
end

always #50 begin
  b=b+1;
  $monitor("%dns monitor: a=%d b=%d sum=%d", $stime, a, b, sum);
end

initial #2000 $finish;

endmodule

11/18上課內容

11/4上課內容

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１位元↑

10/28 3位元多工器

3位元多工器